Alchip teams with Synopsys on 224G PHY-based design for AI data center ASIC bandwidth constraints
SNPS•Interconnect density near theoretical limits
Engineers reported chip-to-chip interconnect bandwidth density near theoretical physical limits within practical die-edge and packaging constraints.
Supports 1.6 Tbps bandwidth with path to 448G SerDes
The design supports up to 1.6 Tbps networking bandwidth, with a path to 448G SerDes implementations.
Focus on bandwidth bottlenecks and packaging constraints
The work targets scale-up and out bandwidth bottlenecks, focusing on die-edge utilization, escape routing, package breakout, signal integrity, and power integrity.
Alchip and Synopsys develop 224G PHY-based design approach
Alchip teamed with Synopsys to develop a protocol-agnostic physical design approach for AI data center ASICs using 224G PHY IP.
