Cadence expands partnership with TSMC on certified tool flows, silicon-proven UALink IP for advanced nodes
CDNS•Cadence expands partnership with TSMC
Cadence expanded its partnership with TSMC to deliver certified design tools and silicon-proven IP for advanced AI and HPC chips.
Support for 3DFabric and multi-chiplet designs
The partnership also supports TSMC 3DFabric wafer-scale and multi-chiplet design flows, including certified die-to-die auto-routing for CoWoS architectures.
Cadence highlighted UALink IP demonstrated on N3P; UCIe-64G taped out on A14; additional IP development extends into Q4 2026.
Tool flows certified for advanced process nodes
Tool flows gained certification for TSMC’s A14, A16, and N2P nodes, targeting faster tape-outs and improved power, performance, and area.
