Cadence, TSMC Expand AI Silicon Collaboration on 3nm and 2nm Nodes
Cadence has expanded its collaboration with TSMC to deliver IP portfolios and signoff-ready EDA flows for AI silicon on TSMC’s N3, N2, A16 and A14 process nodes, aiming to reduce design iterations and accelerate time-to-silicon. Early customer adoption at 3nm and 2nm underscores strong market momentum.
1. Expanded Collaboration Details
Cadence and TSMC have expanded their partnership to provide IP portfolios, signoff-ready end-to-end design infrastructure and certified flows for AI-driven semiconductor development on TSMC’s N3, N2, A16 and A14 process technologies, targeting fewer iterations and improved design-to-correlation for DTCO-focused AI and HPC architectures.
2. Agentic AI Integration in EDA Flows
Under its Design for AI and AI for Design strategy, Cadence is embedding agentic AI into its EDA workflows, enabling goal-driven automation across synthesis, implementation, thermal analysis and signoff stages to accelerate convergence between performance, power and area throughout the chip design cycle.
3. Customer Momentum at 3nm and 2nm
Multiple semiconductor developers and AI infrastructure firms are actively designing on TSMC’s 3nm and 2nm nodes using the expanded IP and certified flows, highlighting strong adoption and confidence in accelerated time-to-silicon for next-generation AI and high-performance computing projects.
4. Silicon-Proven IP and Certified Flows
The collaboration delivers a silicon-proven IP portfolio for N2P—including DDR5 12.8G MRDIMM, PCIe 6.0, LPDDR6/5X 14.4G and HBM4E 16G—and supports advanced implementation systems, thermal solvers, power integrity, extraction, characterization and verification tools, all certified for leading-edge process nodes.