IBM Debuts 0.7 nm Nanostack Chip with 100 Billion Transistors
IBM•IBM unveiled a 0.7 nm chip with three-dimensional nanostack architecture that packs nearly 100 billion transistors on a small die, doubling the density of its 2021 2 nm design. The design delivers up to 50% higher performance and 70% greater energy efficiency, projecting at least a decade of scaling potential.
1. Breakthrough Sub-1 nm Chip
IBM introduced its first sub-1 nm transistor technology at the 0.7 nm node, packing nearly 100 billion transistors on a small die and marking a major advance beyond its 2021 2 nm design.
2. Nanostack Architecture Innovations
The three-dimensional nanostack design vertically stacks and staggers nanosheet transistors, enabling independent material optimization per layer and supporting functional CMOS inverters with demonstrated switching performance.
3. Performance and Efficiency Gains
Technical results project up to 50% higher computational performance and 70% improved energy efficiency compared with the 2 nm node, alongside a 40% SRAM scaling benefit for advanced AI workloads.
4. Roadmap and Adoption Timeline
IBM expects production readiness within five years and foresees at least a decade of further transistor scaling, supported by High NA EUV lithography partnerships and plans for a standalone quantum foundry.
