At CES 2026 in Las Vegas, Intel revealed its Core Ultra Series 3 lineup, featuring six new SKUs across mobile and desktop segments. The highest-end mobile part combines 12 performance cores and 16 efficiency cores with a total of 60MB of L3 cache and Intel’s new Neural Accelerator 2.0. According to Intel, the series delivers up to 10% higher single-threaded performance and 15% better power efficiency compared with the previous generation, while the integrated graphics engine offers up to 30% faster AI inferencing on edge workloads. Intel also showcased OEM designs from Dell and HP that will ship with the new chips in Q2 2026.

During CNBC’s Halftime Report, Kevin Simpson, CIO of Capital Wealth Planning, disclosed that he added Intel to his model portfolio for the first time in 2026, increasing his technology allocation to 22%. Simpson cited the company’s improved execution on both process technology and product launches, pointing to the Core Ultra Series 3 debut and the recent ramp of 4nm server CPUs. His firm expects Intel’s server CPU shipments to grow 8% year-over-year in calendar Q1, driven by enterprise cloud spend, and forecasts Intel’s foundry revenues to rise by mid-teens percentage in the same period.

After an 84.1% stock gain in 2025, some analysts warn that margin compression, geopolitical trade restrictions and legacy 14nm capacity constraints could limit upside in 2026. Intel reported a trailing gross margin of 35.6%, down from 38.2% a year earlier, and expects R&D and capital spending to rise by over 12% as it pushes new nodes into production. Trade tensions with key equipment suppliers in Asia add uncertainty to wafer supply forecasts, while Intel’s own 14A and 18A node rollouts face tighter timelines as the company seeks to regain process leadership by 2028.

Multiple indicators suggest Intel may integrate high-NA EUV lithography into its current 18A manufacturing node, rather than waiting until the publicly stated 14A node in 2028. Intel has publicly disclosed three high-NA machines installed at its Oregon R&D site and reportedly processed 30,000 wafers on them in Q4 2025. Acceptance testing of ASML’s EXE:5200 tool completed in December, meeting volume benchmarks. Insiders at Fab 52 in Arizona have hinted that early single-patterning trials on select 18A layers are already underway, which could yield higher density and better yields compared with triple-patterning on low-NA tools and potentially accelerate Intel’s process roadmap ahead of competitors.