SEALSQ Prioritizes CMOS-Compatible Silicon Spin Qubits and Post-Quantum Security

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SEALSQ has shifted its R&D strategy to semiconductor CMOS-compatible quantum architectures, prioritizing silicon spin qubits and electrons-on-helium platforms to leverage established chipmaking processes. The company is embedding post-quantum cryptography and hardware-based trust mechanisms into its quantum control systems to secure future large-scale silicon-based quantum computers.

1. Strategic Focus on CMOS-Compatible Architectures

SEALSQ has realigned its R&D strategy toward semiconductor CMOS-compatible quantum computing architectures to leverage existing manufacturing ecosystems. This emphasis aims to enable scalable quantum processors by co-designing quantum devices with classical CMOS control circuitry, targeting FDSOI technology for balanced noise reduction and power efficiency.

2. Prioritization of Silicon Spin Qubits and Electrons-on-Helium

The company is concentrating investments on silicon spin qubits, which utilize electrons in silicon chips, and electrons-on-helium platforms, which maintain electrons above superfluid helium on silicon wafers. Both approaches are designed for fabrication and integration with standard chip-making processes to accelerate learning cycles and production readiness.

3. Integration of Post-Quantum Cryptography and Hardware Trust

SEALSQ is embedding post-quantum cryptography algorithms and hardware-based trust mechanisms directly into its quantum control systems. Secure elements integrated alongside qubit control circuitry will enable trusted boot, device attestation, and encrypted communication, ensuring resilience against classical and quantum-enabled attacks as systems scale.

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