Taiwan Semiconductor Manufacturing Company is shifting part of its advanced AI chip output to its Kumamoto site in southern Japan, marking the first time the foundry will mass-produce sub-7-nanometre wafers outside Taiwan. The move targets both risk mitigation—by reducing concentration in a single geography—and faster delivery times for key hyperscale customers. Construction on the new clean-room modules is under way, with pilot runs expected in late 2026 and volume ramp in early 2027.

In the fourth quarter of 2025, TSMC reported revenue of $33.73 billion, up 20.5% from a year earlier, while net income climbed 35% to $15.2 billion. Advanced process technologies at 7 nanometres and below accounted for 77% of wafer revenue, highlighting the company’s leadership in AI silicon. Management has guided Q1 2026 revenue to a range of $34.6 billion to $35.8 billion, signaling continued momentum as AI workloads drive capacity utilization above 95%.

TSMC plans to invest approximately $17 billion to equip its Kumamoto facility for 3-nanometre chip manufacturing, a strategic upgrade from earlier plans focused on mature nodes. The Japanese government has already provided subsidies totaling over ¥500 billion (about $3.7 billion) for initial fab construction; new discussions seek additional incentives to accelerate the 3-nanometre ramp. This second phase is expected to create 2,000 high-skill jobs and secure critical supply for next-generation AI accelerators and mobile SoCs.

By adding capacity in Japan alongside existing Taiwan and Arizona fabs, TSMC is lowering single-region dependency and shortening logistics for distributors in Asia–Pacific. Proximity to major electronics OEMs in Japan offers just-in-time delivery benefits, while diversification supports resilient operations against potential Taiwan-Strait disruptions. The company’s capital expenditure guidance of $32 billion to $36 billion for 2026 reflects substantial allocations to this multi-regional build-out.