AMD Starts Production of 2nm EPYC Venice Chips, Plans Arizona Expansion
AMD•AMD has begun ramping production of its sixth-generation EPYC Venice processors on TSMC’s 2nm node, with initial manufacturing in Taiwan and plans to extend output to Arizona. It also unveiled a second 2nm EPYC chip, Verano, featuring LPDDR memory integration and optimized performance-per-dollar-per-watt for AI and cloud workloads.
1. Production Ramp and Locations
AMD has initiated volume production of its sixth-generation EPYC processors, codenamed Venice, using TSMC’s 2nm process technology. Initial manufacturing is underway in Taiwan, with expansion to TSMC’s Arizona fab planned to increase global supply capacity.
2. Verano Chip Details
Alongside Venice, AMD introduced a second 2nm EPYC processor, Verano, which integrates LPDDR memory directly on-die. This design targets improved performance-per-dollar-per-watt, specifically tuned for cloud computing, enterprise infrastructure and AI workloads.
3. Advanced Packaging Partnership
AMD and TSMC’s collaboration extends into advanced packaging solutions, including SoIC-X and CoWoS-L systems. These packaging technologies enable higher interconnect density and thermal efficiency across AMD’s AI and data center hardware portfolio.
