Testing on MNIST and Fashion-MNIST datasets demonstrated that the FPGA-accelerated simulator achieves runtime reductions of 500× compared to CPU simulations, maintains FPGA logic utilization below 82%, and supports 256 parallel channels while delivering classification accuracy comparable to an optimized Gaussian RBF kernel. HOLO plans to expand simulator capabilities with support for more complex quantum circuits, additional kernel types, and automated circuit-to-hardware mapping compilers, aiming to build multi-node quantum simulation clusters and develop quantum-classical collaborative training mechanisms. MicroCloud Hologram unveiled a quantum AI simulator architecture combining CPUs with FPGAs to accelerate quantum kernel estimation. The design leverages heterogeneous computing and hardware-level optimizations on application-specific quantum kernels for image classification tasks.