Synopsys Achieves M-PHY v6.0 IP Bring-Up on TSMC 2nm, Tapes Out 64G UCIe
Synopsys achieved first silicon bring-up of low-power M-PHY v6.0 IP on TSMC’s N2P node and taped out 64G UCIe and 224G IP for 3nm and 2nm AI chip designs. Its AI-driven EDA flows and 3DIC Compiler boost productivity by up to 5.5× for CoWoS® interposer and multiphysics sign-off.
1. Silicon-Proven IP Milestones
Synopsys reported the industry’s first silicon bring-up of its low-power M-PHY v6.0 IP on TSMC’s N2P process, alongside tape-outs of 64G UCIe and 224G IP to address next-generation AI and high-performance computing bandwidth needs. The company has also achieved first-silicon on PCIe 7.0, HBM4 and LPDDR6/5X across TSMC’s N5, N3P and N2P nodes.
2. AI-Driven EDA Flow Enhancements
Synopsys has integrated AI-powered digital, analog and verification flows into its Fusion Compiler and IC Validator tools, enabling agentic run assistance on TSMC’s A14 NanoFlex™ Pro architecture. These enhancements aim to identify timing and DRC issues earlier, reducing cycle times and improving power, performance and area (PPA) for complex designs.
3. 3D Multi-Die and Multiphysics Enablement
The 3DIC Compiler platform now supports TSMC’s CoWoS® 5.5× reticle interposers, delivering up to 5.5× productivity gains through automated exploration-to-signoff workflows. Integrated multiphysics analysis—from RedHawk-SC electrothermal to HFSS electromagnetic extraction and Ansys photonics simulation—accelerates validation of thermal, power integrity and optical paths in advanced 3D assemblies.
4. Market Position and Growth Outlook
By extending its Foundation IP portfolio across TSMC’s advanced nodes and launching a UCIe IP ASILB solution for automotive SoCs on N5A, Synopsys is positioned to capture growth in AI accelerators, data centers, edge computing and automotive chiplet markets. The collaboration on TSMC’s latest process and packaging technologies strengthens Synopsys’s roadmap for high-performance, energy-efficient system designs.