TSMC Targets 30% Power Reduction and 20% Speed Boost in 2028 A14 Chips
TSM•TSMC forecasts its upcoming A14 generation chips due around 2028 will cut power consumption by up to 30% from its current N2 node while boosting computing performance by over 20%. The contract manufacturer is prioritizing energy-efficient designs through advanced packaging, chip stacking and photonics as it delays next-generation EUV adoption.
1. Energy Efficiency Becomes Primary Design Constraint
Kevin Zhang, Senior Vice President of Business Development, said surging electricity demands from AI workloads are making energy efficiency the main design constraint shaping future chip development as customers seek performance gains without higher power use.
2. Technology Strategies and Roadmap
TSMC plans to cut power consumption by up to 30% between its current N2 node and its A14 generation due around 2028 while delivering over 20% higher computing performance through advanced packaging, chip stacking and photonics, and it will delay next-generation EUV adoption by several years to focus on efficiency improvements.
