Silvaco Launches Mixel MIPI C-PHY/D-PHY IP on TSMC N2P, 25% Fewer Wires
SVCO•Silvaco has made its Mixel MIPI C-PHY/D-PHY combo Universal IP available on TSMC’s N2P process, supporting MIPI D-PHY v3.6 embedded clock mode and C-PHY v2.1 at speeds up to 3.0 Gbps per lane. The IP achieves 25% fewer wires, low power consumption and minimal area, targeting AR glasses and wearables.
1. Product Launch and Availability
Silvaco has released the Mixel MIPI C-PHY/D-PHY combo Universal IP on TSMC’s N2P process, marking its first deployment on industry-leading Nanosheet technology. The IP is available immediately for licensing.
2. Technical Highlights
The physical layer IP supports MIPI D-PHY v3.6 embedded clock mode and C-PHY v2.1 at speeds up to 3.0 Gbps per lane while reducing wire count by 25%. It features low power, low leakage and minimal area.
3. Target Applications
The combo IP is optimized for space-constrained, power-sensitive applications such as AR glasses and wearable devices, where minimal heat dissipation and low EMI are critical. The 25% fewer wires design simplifies routing inside compact form factors.
4. Market Implications
Availability on TSMC’s N2P process extends Silvaco’s advanced IP portfolio into cutting-edge nodes, potentially driving licensing revenue growth. Adoption by device makers leveraging high-performance connectivity standards could enhance Silvaco’s competitive position.
